1. Technical Field
This invention relates generally to mixed signal circuitry and more particularly to phase locked loops.
2. Description of Related Art
Communication systems are known to support wireless and wire lined communications between wireless and/or wire lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS), and/or variations thereof.
Depending on the type of wireless communication system, a wireless communication device, such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, et cetera communicates directly or indirectly with other wireless communication devices. For direct communications (also known as point-to-point communications), the participating wireless communication devices tune their receivers and transmitters to the same channel or channels (e.g., one of the plurality of radio frequency (RF) carriers of the wireless communication system) and communicate over that channel(s). For indirect wireless communications, each wireless communication device communicates directly with an associated base station (e.g., for cellular services) and/or an associated access point (e.g., for an in-home or in-building wireless network) via an assigned channel. To complete a communication connection between the wireless communication devices, the associated base stations and/or associated access points communicate with each other directly, via a system controller, via the public switch telephone network, via the Internet, and/or via some other wide area network.
For each wireless communication device to participate in wireless communications, it includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). As is known, the transmitter includes a data modulation stage, one or more intermediate frequency stages, and a power amplifier. The data modulation stage converts raw data into baseband signals in accordance with a particular wireless communication standard. The one or more intermediate frequency stages mix the baseband signals with one or more local oscillations to produce RF signals. The power amplifier amplifies the RF signals prior to transmission via an antenna.
As is also known, the receiver is coupled to the antenna and includes a low noise amplifier, one or more intermediate frequency stages, a filtering stage, and a data recovery stage. The low noise amplifier receives inbound RF signals via the antenna and amplifies then. The one or more intermediate frequency stages mix the amplified RF signals with one or more local oscillations to convert the amplified RF signal into baseband signals or intermediate frequency (IF) signals. The filtering stage filters the baseband signals or the IF signals to attenuate unwanted out of band signals to produce filtered signals. The data recovery stage recovers raw data from the filtered signals in accordance with the particular wireless communication standard.
FIG. 1 is a schematic block diagram of a prior art phase locked loop. The phase locked loop includes a phase and frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a feedback divider, which may be a fractional-N feedback divider. The phase and frequency detector determines a difference between the phase and/or frequency of a reference oscillation and a feedback oscillation. The charge pump converts the difference signal into a current, which is subsequently converted into a control voltage via the loop filter. The voltage controlled oscillator, based on the control voltage, generates the output oscillation. The feedback divider divides the output oscillation by a divider value (N) to produce the feedback oscillation. As such, in steady state conditions, the output oscillation equals the reference oscillation times the divider value (N).
FIG. 1 further illustrates the output oscillation in the frequency domain to be centered at the output frequency (fOUT). As shown, based on the reference oscillation changing, and/or the divider value changing, the frequency spectrum of the output oscillation has a general shape as shown. The feedback divider divides the output oscillation by the divider value to produce the feedback oscillation. In addition to dividing the frequency by the divider value N, the feedback divider also divides the frequency spectrum of the output oscillation by N thereby producing the narrower frequency spectrum centered at the feedback frequency (fFB).
As shown, the frequency spectrum of the feedback oscillation is compressed with respect to the frequency spectrum of the output oscillation. As such, the phase and frequency detector may lose zero crossings due to the narrower spectrum of the feedback oscillation. When the phase and/or frequency detector loses zero crossings, compensation of the entire loop is adversely effected causing the phase locked loop to have poor frequency tracking, which is a significant problem for radios and other high performance electronic equipment.
FIG. 2 is a schematic block diagram of an alternate prior art phase locked loop that includes the phase and frequency detector, the charge pump, the loop filter and the voltage controlled oscillator. In place of the feedback divider, the phase locked loop of FIG. 2 includes a frequency translator. The frequency translator includes a mixer and a local oscillation wherein the output of the mixer provides the feedback oscillation and corresponds to the difference between the output oscillation (fOUT) and the local oscillation frequency (fLO). In this embodiment, the feedback oscillation has the same spectrum width as the output oscillation. However, the phase locked loop is subject to false locking on an image frequency of the output frequency and local oscillation.
FIG. 3 is a graphical representation of the false locking issue of the phase locked loop of FIG. 2. In this illustration, the desired output oscillation has a frequency at (fOUT). The local oscillation has a frequency of (fLO). Accordingly, the difference between the output oscillation and the local oscillation corresponds to the reference oscillation, which corresponds to the frequency of the feedback oscillation. However, due to the frequency translation nature of a mixer, an image frequency is also generated which corresponds to the local oscillation frequency less the difference between the output oscillation frequency and the local oscillation frequency. As such, as the phase locked loop of FIG. 2 is approaching steady state condition, the output oscillation is increasing from a lower frequency to a higher frequency. Once the output oscillation reaches the frequency that corresponds to the image frequency (fIMAGE), the phase locked loop locks at this frequency if the VCO is not saturated at this frequency. As such, the desired output oscillation is never achieved.
FIG. 4 illustrates one solution for avoiding the phase locked loop of FIG. 2 falsely locking at the image frequency. In this solution, the difference between the frequency of the local oscillator and the frequency of the desired output oscillation is increased to a range such that the local oscillation frequency is outside of the bandwidth of the VCO. As such, as the output oscillation is increasing, when it hits the image frequency, the voltage controlled oscillator is still outside of its linear range of operation, (i.e., is saturated in the full on mode) such that the phase locked loop does not lock at the image frequency. While this avoids false locking, it presents many issues for high frequency operations. In particular, using crystal reference oscillators above approximately 20-25 megahertz substantially increases the cost of such phase locked loops. In addition, if the phase locked loop is implemented in CMOS technology, it is difficult to produce a reliable high frequency phase and frequency detector that operates above a 100 megahertz.
Therefore, a need exists for a phase locked loop that avoids false locking while allowing conventional and economical components to be used.
The phase locked loop that avoids false locking of the present invention substantially meets these needs and others. In one embodiment, a phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The difference signal corresponds to the phase and/or frequency difference between the feedback oscillation and the reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. For example, the control signal may be a voltage controlled signal where the controlled oscillation module is a voltage controlled oscillator. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.
In another embodiment, a phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, a frequency translation module, and a divider module. The difference detector produces a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter converts the difference signal into a control signal. The controlled oscillation module produces an output oscillation based on the control signal. The frequency translation module and the divider module, in combination, produce an intermediate feedback oscillation from the output oscillation and then produce the feedback oscillation from the intermediate feedback oscillation. The intermediate feedback oscillation is of a frequency, with respect to the reference oscillation and the output oscillation, to substantially avoid false locking of the phase locked loop.
The phase locked loop of the present invention may be used in a variety of applications. For example, the phase locked loop may be included in a phase shift keying (PSK) modulator that includes a modulation module to mix data with the translation oscillation to produce the feedback oscillation. Further, the phase locked loop and/or the PSK modulator may be used in a radio frequency integrated circuit.